|
課程名稱 |
積體電路測試
Vlsi Testing |
|
開課學期 |
104-1 |
|
授課對象 |
電機資訊學院 電子工程學研究所 |
|
授課教師 |
李建模 |
|
課號 |
EEE5001 |
|
課程識別碼 |
943EU0010 |
|
班次 |
|
|
學分 |
3 |
|
全/半年 |
半年 |
|
必/選修 |
選修 |
|
上課時間 |
星期二2,3,4(9:10~12:10) |
|
上課地點 |
電二146 |
|
備註 |
本課程以英語授課。
總人數上限：60人 |
|
Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1041_vlsitest |
|
課程簡介影片 |
|
|
核心能力關聯 |
核心能力與課程規劃關聯圖 |
|
課程大綱
|
|
為確保您我的權利,請尊重智慧財產權及不得非法影印
|
|
課程概述 |
本課程介紹數位積體電路測試之觀念及技術，適合對VLSI/EDA有興趣的同學修習。
1. Overview
2. Logic simulation
3. Fault modeling
4. Fault simulation
5. Testability analysis
6. Combinational ATPG
7. Sequential ATPG
8. Delay fault testing
9. Diagnosis
10. Built-in Self Test
11. Test Compression
12. Design for Testability |
|
課程目標 |
provide basic knowledge in VLSI testing. |
|
課程要求 |
成績評量方式
Homework: 30% (including programming assignments)
Exam: 30%
Term Project: 35%
Class Participation 5%
預修課程
交換電路與邏輯設計（or equivalent）
計算機程式 |
|
預期每週課後學習時數 |
|
|
Office Hours |
|
|
指定閱讀 |
|
|
參考書目 |
教科書：
參考書目： Wang, Wu, Wen, "VLSI Test Principles and Architectures, Morgan Kuffman, 2006.
M.L. Bushnell, V.D. Agrawal, “Essentials of Electronic Testing,” Kluwer Academic Publishers, 2000.
M. Abramovici, M.A. Breuer, and A.D. Frideman, “Digital Systems Testing and Testable Design,” IEEE Press 1995.
|
|
評量方式
(僅供參考) |
|
|
週次 |
日期 |
單元主題 |
|
Week 1 |
|
Introduction |
|
Week 2 |
|
Logic Simulation, Fault modeling |
|
Week 3 |
|
Fault Models, Fault collapsing |
|
Week 4 |
|
no class |
|
Week 5 |
|
Fault Simulation |
|
Week 6 |
|
Testability; Combinational ATPG |
|
Week 7 |
|
Seq. ATPG; Delay tests |
|
Week 8 |
|
Test compress |
|
Week 9 |
|
Diagnosis |
|
Week 10 |
|
Test Compression; DFT |
|
Week 11 |
|
DFT(II) |
|
Week 12 |
|
BIST (I) |
|
Week 13 |
|
BIST (II) |
|
Week 14 |
|
Project progress presentation; Test Compression; Memory Test |
|
Week 15 |
|
Functional tests |
|
Week 16 |
|
Defect based testing |
|
Week 17 |
|
Final Exam |
|
Week 18 |
|
project presentation
(submit report in class) |
|